1. Field of Invention
The invention relates to a method for patterning a substrate and, in particular, a method for patterning a substrate with mechanically robust, high aspect ratio features in a spin-on layer.
2. Description of Related Art
In material processing methodologies, such as those used in the fabrication of micro-electronic devices, pattern etching is often utilized to define the intricate patterns associated with various integrated circuit elements. Pattern etching comprises preparing a pattern in a layer of photo-sensitive material, such as photo-resist, using lithographic patterning, and transferring the pattern formed in the layer of photo-sensitive material to the substrate by etching.
The lithographic patterning of the photo-sensitive material generally involves coating an upper surface of the substrate with a thin film of photo-sensitive material and then exposing the thin film of photo-sensitive material to a pattern of radiation by projecting radiation from a radiation source through a mask using, for example, a photolithography system. Thereafter, a developing process is performed, during which the removal of the irradiated regions of the photo-sensitive material occurs (as in the case of positive-tone photo-resist), or the removal of non-irradiated regions occurs (as in the case of negative-tone photo-resist). The remaining photo-sensitive material exposes the underlying substrate surface to a pattern that is ready to be etched into the surface.
Typically, this pattern may be transferred to a hard mask layer, which provides greater etch resistance for pattern transfer to more critical, underlying layers, such as insulation layers in metal interconnects for back-end-of-line (BEOL) operations, or transistor gate stacks for front-end-of-line (FEOL) operations. One hard mask material in common use today includes amorphous carbon, which is deposited using chemical vapor deposition (CVD) or variations thereof. However, lithographic patterning schemes that incorporate amorphous carbon layers as a hard mask layer suffer from high cost of ownership (CoO), low productivity, and particle contamination, to name a few disadvantages.
Therefore, more recently, spin-on materials have gained some popularity in lithographic patterning schemes even though these spin-on materials are perceived to be less etch resistant and less mechanically robust when subjected to other process steps in micro-electronic device fabrication process flows. The latter handicap is only exacerbated as feature sizes shrink to accommodate the increasing demand for smaller, faster micro-electronic devices. In particular, the requirements imposed upon lithographic patterning schemes, as described above, only become more challenging in an effort to avoid catastrophic failure, such as pattern collapse.
Moreover, while material processing technology has enabled a significant reduction in the lateral dimensions of these features, the thickness of layers or the height of structures decreases at a lesser rate, thus, leading to an escalating aspect ratio for these features. The increased aspect ratio combined with the decreased lateral dimension, particularly in lithographic layers, has only increased the susceptibility to the aforementioned failures. For example, when high aspect ratio features are patterned in spin-on layers, pattern collapse may occur resulting from an imbalance in surface tensile stress imposed during wet cleaning process steps.